View PR31700_4360568.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PR31700 32-bit risc microprocessor preliminary specification supersedes data of 1997 dec 15 1998 may 13 integrated circuits
philips semiconductors preliminary specification PR31700 32-bit risc microprocessor 2 1998 may 13 general description the PR31700 is a single-chip digital assp (application specific stand product) used in hpcs (handheld personal computers), palm-size pcs, screenphones, smartphones, and other vertical market applications in the mobile computing and communication markets. the PR31700 consists of system support logic, integrated with the pr3901 processor core designed by philips semiconductors. features ? r3000a-based pr3901 processor core risc architecture developed by mips technologies, inc. philips has added its own multiply-add and branch-likely instructions. a single-cycle multiply/accumulate module to allow integrated dsp functions, such as a software modem for high-performance standard data and fax protocols instruction cache: 4k bytes; data cache: 1k bytes on-chip translation lookaside buffer (tlb) with 3264-bit wide entries, each of which maps 4kbyte page max 75mhz operation ? built-in peripheral circuit clock generator with built-in eightfold-frequency phase-locked loop (pll) four-stage write buffer a high performance and flexible bus interface unit multiple dma channels memory controller for dram, hdram, sdram, sram, rom, flash memory and pcmcia power management unit big / little endian ? low power dissipation 3.3v operation standby current 10a(typ) cpu clock stop mode power down modes for individual internal peripheral modules ? plastic lqfp 208-pin package the information contained herein is subject to change without notice. philips is continually working to improve the quality and the reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it i s the responsibility of the buyer, when utilizing philips products, to observe standards of safety, and to avoid situations in which a malf unction or failure of a philips product could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that philips products are used within specified operating ranges as s et forth in the most recent products specifications. also, please keep in mind the precautions and conditions set forth in the philips semiconductor reliability handbook the information contained herein is presented only as a guide for the applications of our products. no responsibility is assume d by philips for any infringements of patents or other rights of the third parties which may result from its use. no license is granted by impli cation or otherwise under any patent or patent rights of philips or others. r3000a is a trademark of mips technologies, inc.
philips semiconductors preliminary specification PR31700 32-bit risc microprocessor 1998 may 13 3 system configuration sn00183 3.3v sysclk PR31700 (208pin pqfp) isdn or other peripherals high speed serial port touchscreen (resistive) lcd ir id rom power supply 132 mbytes(s) dram 164 mbytes rom 12 pcmcia slots 32khz main thermistor backup (lithium) ac adapter 3.3v phone jack daa or daa pr3901 risc cpu core dram/sdram interface pcmcia/rom/i/f timers realtime clock serial i/f lcd interface tlb icache/ ram ram icache/ 32bit bus t betty ucb1200 (analog asic) 44pin qfp figure 1. system block diagram
philips semiconductors preliminary specification PR31700 32-bit risc microprocessor 1998 may 13 4 sn00184 sib module to betty to lcd to general purpose i/o 32 khz sysclk video module io module timer module (+ rtc) clock module system interface module (sim) chi module ir module uart module (dual uart) spi module power module interrupt module to power supply to uart to ir to high speed serial control addr data to memory data addr pr3901 risc cup core data addr data addr r3901 processor core data addr icache 4 kbyte dcache 1 kbyte mac system interface unit (siu) module arbitration/ dma/adr decode bus interface unit (biu) module (s) dram/pcmcia/rom figure 2. PR31700 block diagram
philips semiconductors preliminary specification PR31700 32-bit risc microprocessor 1998 may 13 5 memory connections sn00185 big endian PR31700 bank0 bank1 d(15:0) data 16bit dram cashi* caslo* ras* we* addr a(12:0) we* raso* 133 d[31] 145 d[24] a[12:0] 169 we* 194 ras0* 199 cas0* 198 cas1* 197 cas2* 195 cas3* 2 d[0] 14 d[7] 16 d[8] 27d[16] 159 d[16] 146 d[23] d[31] d[24] a[12:0] we* ras0* cas0* cas1* cas2* cas3* d[0] d[7] d[8] d[15] d[16] d[23] a(12:0) we* ras0* cas0* cas1* cas2* cas3* cas lo* cas ml* cas mh* cas hi* addr we* ras* 32bit cas1* cas0* pin no. d(31:0) data figure 3. memory connections
philips semiconductors preliminary specification PR31700 32-bit risc microprocessor 1998 may 13 6 pin assignments no. i/o signal name no. i/o signal name no. i/o signal name 1 vdd 41 i sibdin 81 vss 2 i/o d[0] 42 o sibdout 82 o pwrcs 3 vss 43 vdd 83 i pwrlnt 4 i/o d[1] 44 i sibirq 84 i pwrok 5 i/o d[2] 45 i/o miox[0] 85 nc 6 vdd 46 i/o io[6] 86 i onbutn 7 i/o d[3] 47 i/o io[5] 87 i pon 1 8 vss 48 vss 88 i cpures * 9 i/o d[4] 49 i/o chiclk 89 vdd 10 vdd 50 i/o chifs 90 o dispon 11 i/o d[5] 51 i chidin 91 o frame 12 i/o d[6] 52 o chidout 92 vss 13 vss 53 vdd 93 o df 14 i/o d[7] 54 i rxd 94 o load 15 vss 55 o txd 95 o cp 16 i/o d[8] 56 i/o io[4] 96 vss 17 vdd 57 nc 97 vdd 18 i/o d[9] 58 i irin 98 o vdat[0] 19 i/o d[10] 59 o irout 99 o vdat[1] 20 vss 60 vss 100 o vdat[2] 21 i/o d[11] 61 vdd 101 o vdat[3] 22 vdd 62 i cardet 102 vss 23 i/o d[12] 63 o rxpwr 103 i/o io[1] 24 i/o d[13] 64 i/o io[3] 104 vdd 25 vss 65 i/o io[2] 105 i card2wait 8 26 i/o d[14] 66 vss 106 o card2csh * 27 i/o d[15] 67 o spiclk 107 o card2csl * 28 vdd 68 i spiin 108 i/o io[0] 29 i endian 69 o spiout 109 vss (pll) 30 i/o miox[1] 70 vdd 110 o cardiord * 31 i rsrv1 71 i testcpu 111 o cardiowr * 32 i/o nc 72 i testin 112 o cardreg * 33 vss 73 o viddone 113 i card1wait * 34 i/o nc 74 i testaiu 114 vdd (pll) 35 vdd 75 vss 115 o carddir * 36 vdd 76 i vcc3 116 vdd 37 o sibmclk 77 o bc32k 117 o card1csl * 38 vss 78 vdd 118 o card1csh * 39 o sibsclk 79 i c32kln 119 vss 40 o sibsync 80 o c32kout 120 o mcs3 1
philips semiconductors preliminary specification PR31700 32-bit risc microprocessor 1998 may 13 7 pin assignments (continued) no. i/o signal name no. i/o signal name no. i/o signal name 121 o mcs2 2 161 - nc 201 - vdd 122 o mcs1 2 162 o cs0 * 202 o dcke 123 o mcs0 2 163 o rd * 203 - vss 124 o cs3 2 164 - vss 204 i dclkin 125 o cs2 2 165 - vdd 205 o dclkout 126 o cs1 2 166 o dgrnt * 206 - vdd 127 - vdd 167 i dreq * 207 o dqmh 128 i sysclkin 168 o ale 208 o dqml 129 o sysclkout 169 o we * 130 - vss 170 - vdd 131 - vss 171 i/o a[12] 132 - vdd 172 i/o a[11] 133 i/o d[31] 173 - vss 134 i/o d[30] 174 i/o a[10] 135 - vss 175 i/o a[9] 136 i/o d[29] 176 - vdd 137 - vdd 177 i/o a[8] 138 i/o d[28] 178 i/o a[7] 139 i/o d[27] 179 - vss 140 - vss 180 i/o a[6] 141 i/o d[26] 181 i/o a[5] 142 - vss 182 - vdd 143 i/o d[25] 183 i/o a[4] 144 - vdd 184 - vss 145 i/o d[24] 185 i/o a[3] 146 i/o d[23] 186 i/o a[2] 147 - vdd 187 - vdd 148 i/o d[22] 188 i/o a[1] 149 - vss 189 i/o a[0] 150 i/o d[21] 190 - vss 151 - vdd 191 - vss 152 i/o d[20] 192 o dcs0 * 153 i/o d[19] 193 o ras1 8 154 - vss 194 o ras0 * 155 i/o d[18] 195 o cas3 * (cas0 * ) 156 - vdd 196 - vdd 157 i/o d[17] 197 o cas2 * (cas1 * ) 158 - vss 198 o cas1 * (cas2 8 ) 159 i/o d[16] 199 o cas0 8 (cas3 * ) 160 - vdd 200 - vss
philips semiconductors preliminary specification PR31700 32-bit risc microprocessor 1998 may 13 8 pin functions name i/o functions memory pins d(31:0) i/o these pins are the data bus for the system. 8-bit sdrams should be connected to bits 7:0 and 16-bit sdrams and drams should be connected to bits 15:0. all other 16-bit ports should be connected to bits 31:16. of course, 32-bit ports should be connected to bits 31:0. these pins are normally outputs and only become inputs during reads, thus no resistors are required since the bus will only float for a short period of time during bus turn-around. a(12:0) o these pins are the address bus for the system. the address lines are multiplexed and can be connected directly to sdram and dram devices. to generate the full 26-bit address for static devices, an external latch must be used to latch the signals using the ale signal. for static devices, address bits 25:13 are provided by the external latch and address bits 12:0 (directly connected from PR31700's address bus) are held afterward by PR31700 processor for the remainder of the address bus cycle. ale o this pin is used as the address latch enable to latch a(12:0) using an external latch, for generating the upper address bits 25:13. rd * o this pin is used as the read signal for static devices. this signal is asserted for reads from /mcs3*-0*, /cs3*-0*, /card2cs* and /card1cs* for memory and attribute space, and for reads from PR31700 processor accesses if showposeidon is enabled (for debugging purposes). we* o this pin is used as the write signal for the system. this signal is asserted for writes to /mcs3*-0*, /cs3*-0*, /card2cs* and /card1cs* for memory and attribute space, and for writes to dram and sdram. cas0 * (/we0) * o this pin is used as the cas signal for sdrams, the cas signal for d(7:0) for drams, and the write enable signal for d(7:0) for static devices. cas * (/we1) * o this pin is used as the cas signal for d(15:8) for drams and the write enable signal for d(15:8) for static devices. cas2 * (/we2) * o this pin is used as the cas signal for d(23:16) for drams and the write enable signal for d(23:16) for static devices. cas3 * (/we3) * o this pin is used as the cas signal for d(31:24) for drams and the write enable signal for d(31:24) for static devices. ras0 * o this pin is used as the ras signal for sdrams and the ras signal for bank0 drams. ras1 * (/dcs1) * o this pin is used as the chip select signal for bank1 sdrams and the ras signal for bank1 drams. dcs0 * o this pin is used as the chip select signal for bank0 sdrams. dcke o this pin is used as the clock enable for sdrams. dclkin i this pin must be tied externally to the dclkout signal and is used to match skew for the data input when reading from sdram and dram devices. dclkout o this pin is the (nominal) 73.728 mhz clock for the sdrams. dqmh o this pin is the upper data mask for a 16-bit sdram configuration. dqml o this pin is the lower data mask for a 16-bit sdram or 8-bit sdram configuration. cs30 * o these pins are the chip select 3 through 0 signals. they can be configured to support either 32-bit or 16-bit ports. mcs30 * o these pins are the memory card chip select 3 through 0 signals. they only support 16-bit ports. card2csh * ,l * o these pins are the chip select signals for pcmcia card slot 2. /card1csh * ,l * o these pins are the chip select signals for pcmcia card slot 1. cardreg * o this pin is the /reg* signal for the pcmcia cards. cardiord * o this pin is the /iord* signal for the pcmcia io cards. cardiowr * o this pin is the /iowr* signal for the pcmcia io cards. carddir * o this pin is used to provide the direction control for bi-directional data buffers used for the pcmcia slot(s). this signal will assert whenever /card2csh* or /card2csl* or /card1csh* or /card1csl* is asserted and a read transaction is taking place. card2wait * i this pin is the card wait signal from pcmcia card slot 2. card1wait * i this pin is the card wait signal from pcmcia card slot 1. *active-low signal
philips semiconductors preliminary specification PR31700 32-bit risc microprocessor 1998 may 13 9 name i/o functions bus arbitration pins dreq* i this pin is used to request external arbitration. if the testsiu signal is high and the testsiu function has been enabled, then once /dgrnt* is asserted, external logic can initiate reads or writes to PR31700 processor registers by driving the appropriate input signals. if the testsiu signal is low or the testsiu function has not been enabled, then PR31700 memory transactions are halted and certain memory signals will be tri-stated when /dgrnt* is asserted in order to allow an external master to access memory. dgrnt* o this pin is asserted in response to /dreq* to inform the external test logic or bus master that it can now begin to drive signals. *active-low signal name i/o functions clock pins sysclkin i this pin should be connected along with sysclkout to an external crystal which is the main PR31700 clock source. sysclkout o this pin should be connected along with sysclkin to an external crystal which is the main PR31700 clock source. c32kin i this pin along with c32kout should be connected to a 32.768 khz crystal. c32kout o this pin along with c32kin should be connected to a 32.768 khz crystal. bc32k o this pin is a buffered output of the 32.768 khz clock. name i/o functions chi pins chifs i/o this pin is the chi frame synchronization signal. this pin is available for use in one of two modes. as an output, this pin allows PR31700 to be the master chi sync source. as an input, this pin allows an external peripheral to be the master chi sync source and the PR31700 chi module will slave to this external sync. chiclk i/o this pin is the chi clock signal. this pin is available for use in one of two modes. as an output, this pin allows PR31700 to be the master chi clock source. as an input, this pin allows an external peripheral to be the master chi clock source and the PR31700 chi module will slave to this external clock. chidout o this pin is the chi serial data output signal. chidin i this pin is the chi serial data input signal. name i/o functions io pins io(6:0) i/o these pins are general purpose input/output ports. each port can be independently programmed as an input or output port. each port can generate a separate positive and negative edge interrupt. each port can also be independently programmed to use a 16 to 24 msec debouncer. mio(1:0) i/o these pins are multi-function input/output ports. each port can be independently programmed as an input or output port, or can be programmed for multi-function use to support test signals (for debugging purposes only). each port can generate a separate positive and negative edge interrupt. note that 30 other multi-function pins are available for usage as multi-function input/output ports. these pins are named after their respective standard/normal function and are not listed here. name i/o functions reset pins /cpures* i this pin is used to reset the cpu core. this pin should be connected to a switch for initiating a reset in the event that a software problem might hang the cpu core. the pin should also be pulled up to vstandby* through an external pull-up resistor. /pon* i this pin serves as the power on reset signal for PR31700. this signal must remain low when vstandby is asserted until vstandby is stable. once vstandby is asserted, this signal should never go low unless all power is lost in the system. vstandbyethis signal provides power for the PR31700 and other components in the system that must never lose power. this signal should always be asserted if there is eithr a good main backup battery, or if a battery charger is plugged in.
philips semiconductors preliminary specification PR31700 32-bit risc microprocessor 1998 may 13 10 name i/o functions power supply pins onbutn i this pin is used as the on button for the system. asserting this signal will cause pwrcs to set to indicate to the system power supply to turn power on to the system. pwrcs will not assert if the pwrok signal is low. pwrcs o this pin is used as the chip select for the system power supply. when the system is off, the assertion of this signal will cause the system power supply to turn vccdram and vcc3 on to power up the system. the power supply will latch spi commands on the falling edge of pwrcs. pwrok i this pin provides a status from the system power supply that there is a good source of power in the system. this signal typically will be asserted if there is a battery charger supplying current or if the main battery is good and the battery door is closed. if pwrok is low when the system is powered off, pwrcs will not assert as a result of the user pressing the onbutn or an interrupt attempting to wake up the system. if the device is on when the pwrok signal goes low, the software will immediately shut down the system since power is about to be lost. when pwrok goes low, there must be ample warning so that the software can shut down the system before power is actually lost. pwrint i this pin is used by the system power supply to alert the software that some status has changed in the system power supply and the software should read the status from the system power supply to find out what has changed. these will be low priority events, unlike the pwrok status, which is a high priority emergency case. vcc3 i this pin provides the status of the power supply for the rom, ucb1200, system buffers, and other transient components in the system. this signal will be asserted by the system power supply when pwrcs is asserted, and will always be turned off when the system is powered down. v cc dram: this signal provides power for the dram and/or sdram. the supply must be off when vstandby is first asserted, andremain off until the system is powered up by the assertion of pwrcs. when the software subsequently powers down the system it may choo se to keep this supply on to preserve the contents of memory. name i/o functions sib pins sibdin i this pin contains the input data shifted from ucb1200 and/or external codec device. sibdout o this pin contains the output data shifted to ucb1200 and/or external codec device. sibsclk o this pin is the serial clock sent to ucb1200 and/or external codec device. the programmable sibsclk rate is derived by dividing down from sibmclk. sibsync o this pin is the frame synchronization signal sent to ucb1200 and/or external codec device. this frame sync is asserted for one clock cycle immediately before each frame starts and all devices connected to the sib monitor sibsync to determine when they should transmit or receive data. sibirq i this pin is a general purpose input port used for the sib interrupt source from ucb1200. this interrupt source can be configured to generate an interrupt on either a positive and/or negative edge. sibmclk i/o this pin is the master clock source for the sib logic. this pin is available for use in one of two modes. first, sibmclk can be configured as a high-rate output master clock source required by certain external codec devices. in this mode all sib clocks are synchronously slaved to the main PR31700 system clock clk2x. conversely, sibmclk can be configured as an input slave clock source. in this mode, all sib clocks are derived from an external sibmclk oscillator source, which is asynchronous with respect to clk2x. also, for this mode, sibmclk can still be optionally used as a high-rate master clock source required by certain external codec devices. name i/o functions spi pins spiclk o this pin is used to clock data in and out of the spi slave device. spiout o this pin contains the data that is shifted into the spi slave device. spiin i this pin contains the data that is shifted out of the spi slave device. name i/o functions uart and ir pins txd o this pin is the uart transmit signal from the uart a module. rxd i this pin is the uart receive signal to the uart a module.
philips semiconductors preliminary specification PR31700 32-bit risc microprocessor 1998 may 13 11 name functions i/o irout o this pin is the uart transmit signal from the uart b module or the consumer ir output signal if consumer ir mode is enabled. irin i this pin is the uart receive signal to the uart b module. rxpwr o this pin is the receiver power output control signal to the external communication ir analog circuitry. cardet i this pin is the carrier detect input signal from the external communication ir analog circuitry. name i/o functions video pins frame o this pin is the frame synchronization pulse signal between the video module and the lcd, and is used by the lcd to return it's pointers to the top of the display. the video module asserts frame after all the lines of the lcd have been shifted and transferred, producing a full frame of display. df o this pin is the ac signal for the lcd. since lcd plasma tends to deteriorate whenever subjected to a dc voltage, the df signal is used by the lcd to alternate the polarity of the row and column voltages used to turn the pixels on and off. the df signal can be configured to toggle on every frame or can be configured to toggle every programmable number of load signals. load o this pin is the line synchronization pulse signal between the video module and the lcd, and is used by the lcd to transfer the contents of it's horizontal line shift register to the lcd panel for display. the video module asserts load after an entire horizontal line of data has been shifted into the lcd. cp o this pin is the clock signal for the lcd. data is pushed by the video module on the rising edge of cp and sampled by the lcd on the falling edge of cp. vdat(3:0) o these pins are the data for the lcd. these signals are directly connected to the lcd for 4-bit non-split displays. for 4-bit split and 8-bit non-split displays, an external register is required to demultiplex the 4-bit data into the desired 8 parallel data lines needed for the lcd. dispon o this pin is the display-on enable signal for the lcd. viddone o this pin is used to externally synchronize events to periods whenthe vido is not shifting. name i/o functions endian pin endian i this pin is used to select the endianess of the PR31700. the o1o level input sets the endianess to the big endian, while the o0o level input tot he little endian. name i/o functions test pins testsiu i this pin allows external logic to initiate read or write transactions to PR31700 registers. the testsiu mode is enabled by toggling this signal after the device has powered up. once the function is enabled, if the testsiu pin is high when the bus is arbitrated (using /dreq and /dgrnt), then external logic can initiate read and write transactions to PR31700 registers. this pin is used for debugging purposes only. testcpu i this pin allows numerous internal cpu core signals to be brought to external PR31700 pins, in place of the normal signals assigned to these pins. the cpu core signals assigned to their respective pins during testcpu mode are vendor-dependent. the testcpu mode is enabled by asserting this testcpu signal, and this function is provided for generating test vectors for the cpu core. this pin is used for debugging purposes only. testin i this pin is reserved for vendor-dependent use. this pin is used for debugging purposes only. viddone o this signal is used to synchronize ucb1200 to read touchscreen input, when there is no video data shifted into lcd panel. name i/o functions spare pins nc51 no connect these pins are reserved for future use and should be left unconnected. rsrv1 i these pins are reserved for future use and should be connected to ground.
philips semiconductors preliminary specification PR31700 32-bit risc microprocessor 1998 may 13 12 name i/o functions power supply pins v dd (33 each) v these pins are the power pins for PR31700 and should be connected to the digital +3.3v power supply vstandby. v ss (33 each) g these pins are the ground pins for PR31700 and should be connected to digital ground. note: for some vendor-dependent implementations of PR31700, pin 131 may be used for a filter capacitor for the sysclk oscillator (capacitor connected between pin 131 and digital ground). v dd (for pll) v this pin is the analog power pin for the PR31700. keep away from other v dd . v ss (for pll) g this pin is the analog ground pin for the PR31700. keep away from other v ss .
philips semiconductors preliminary specification PR31700 32-bit risc microprocessor 1998 may 13 13 pin usage information this section contains tables summarizing various aspects of the pin usage for the PR31700. table 1 lists the standard versus multi-function usage for each PR31700 pin, if applicable. those signal names shown in parentheses are test signals for debugging purposes only. the column showing the multi-function select signal and reset state indicates the internal control signal used to select the multi-function mode, as well as the default configuration of each multi-function pin during reset. the obus arb stateo column shows which pins are tri-stated whenever the dgrnt* signal is asserted in response to a dreq*(external bus arbitration request). table 1. PR31700 standard and multi-function pin usage PR31700 pin standard function (i = input, o = output) multi-function multi-function select (reset state: 1 = multi-function mode selected; 0 = standard function & mode selected) bus arb state d[31:0] d[31:0] (i/o) hi-z a[12:0] a[12:0] (i/o) ale ale (o) hi-z rd* rd* (o) hi-z we* we* (o) hi-z cas0* (we0*) cas0* (o) hi-z cas1* (we1*) cas1* (o) hi-z cas2* (we2*) cas2* (o) hi-z cas3* (we3*) cas3* (o) hi-z ras0* ras0* (o) hi-z ras1* (dcs1*) ras1* (o) hi-z dcs0* dcs0* (o) hi-z dcke dcke (o) hi-z dclkin dclkin (i) dclkout dclkout (o) hi-z dqmh dqmh (o) hi-z dqml dqml (o) hi-z dreq* dreq* (i) mio[27] miosel[27] (0) dgrnt* dgrnt* (o) mio[26] miosel[26] (0) sysclkin sysclkin (i) sysclkout sysclkout (o) c32kln c32kin (i) c32kout c32kout (o) bc32k bc32k(o) mio[25] miosel[25] (1) vdat[3] vdat[3] (o) (berr) irqtest (0) vdat[2] vdat[2] (o) vdat[1] vdat[1] (o) (irqhigh) irqtest (0) vdat[0] vdat[0] (o) (irqlow) irqtest (0) cp cp (o) load load (o) df df (o) frame frame (o)
philips semiconductors preliminary specification PR31700 32-bit risc microprocessor 1998 may 13 14 table 1. PR31700 standard and multi-function pin usage (continued) PR31700 pin standard function (i = input, o = output) multi-function multi-function select (reset state: 1 = multi-function mode selected; 0 = standard function & mode selected) bus arb state dispon dispon (o) pwrcs pwrcs (o) pwrint pwrint (i) pwrok pwrok (i) onbutn onbutn (i) cpures* cpures* (i) pon* pon* (i) txd txd (o) mio[24] miosel[24] (0) rxd rxd (i) mio[23] miosel[23] (0) cs0* cs0* (o) hi-z cs1* cs1* (o) mio[22] miosel[22] (0) cs2* cs2* (o) mio[21] miosel[21] (0) cs3* cs3* (o) mio[20] miosel[20] (0) mcs0* mcs0* (o) mio[19] miosel[19] (1) mcs1* mcs1* (o) mio[18] miosel[18] (1) mcs2* mcs2* (o) mio[17] miosel[17] (1) mcs3* mcs3* (o) mio[16] miosel[16] (1) chifs chifs (i/o) mio[31] miosel[31] (1) chiclk chiclk (i/o) mio[30] miosel[30] (1) chidout chidout (o) mio[29] miosel[29] (1) chidin chidin (i) mio[28] miosel[28] (1) vcc3 vcc3 (i) io6 io6 (i/o) io5 io5 (i/o) io4 io4 (i/o) io3 io3 (i/o) io2 io2 (i/o) io1 io1 (i/o) io0 io0 (i/o) spiclk spiclk (o) mio[15] miosel[15] (0) spiout spiout (o) mio[14] miosel[14] (0) spiin spiin (i) mio[13] miosel[13] (0) sibsync sibsync (o) sibdout sibdout (o) sibdin sibdin (i) sibmclk sibmclk (i/o) mio[12] miosel[12] (0)
philips semiconductors preliminary specification PR31700 32-bit risc microprocessor 1998 may 13 15 table 1. PR31700 standard and multi-function pin usage (continued) PR31700 pin standard function (i = input, o = output) multi-function multi-function select (reset state: 1 = multi-function mode selected; 0 = standard function & mode selected) bus arb state sibsclk sibsclk (o) sibirq sibirq (i) rxpwr rxpwr (o) cardet cardet (i) irout irout (o) irin irin (i) testaiu testaiu (i) testcpu testcpu (i) testin testin (i) viddone viddone (o) cardreg* cardreg*(o) (showdino / cs*) mio[11] miosel[11] (1) cardiowr* cardiowr* (o) mio[10] miosel[10] (1) cardiord* cardiord* (o) mio[9] miosel[9] (1) card1csl* card1csl* (o) mio[8] miosel[8] (1) card1sch* card1csh* (o) mio[7] miosel[7] (1) card2csl* card2csl* (o) mio[6] miosel[6] (1) card2csh* card2csh* (o) mio[5] miosel[5] (1) card1wait* card1wait* (i) mio[4] miosel[4] (1) card2wait* card2wait* (i) mio[3] miosel[3] (1) carddir* carddir* (o) miox[2] miosel[2] (1) miox[1] (master) miox[1] miosel[1] (1) miox[0] (insfetch*) miox[0] miosel[0] (1) endian endian (i) nc[5:1] spare rsrv1 spare (i) vdd34 pins + 3.3 v vss34 pins gnd
philips semiconductors preliminary specification PR31700 32-bit risc microprocessor 1998 may 13 16 table 2 lists various power-down states and conditions for each PR31700 pin. the opower-down controlo column shows the conditio ns which trigger a power-down for each respective pin. this column also shows the reset state for each of these conditions. the opon* stateo column defines the state of each pin at power-on reset (pon*). this condition is defined as i nitial power up of the PR31700, whereby the PR31700 is initialized and the PR31700 pins are reset to the state shown in the table. this state is entered after power is applied for the very first time (vstandby is turned on but vcc3 is still turned off). the o1st-time power-up stateo column defines the state of each pin after power-up mode (running state) is exec uted for the first time. this mode is defined as vcc3 applied to the entire system and is initiated by the user pressing the onbutn while in the power-on reset (pon*) state. note that the defined state of various pins for 1st-time power-up may depend on the configuration of external devices attached to these pins. after 1st-time power-up, the software could change the state of va rious pins to be different from those shown in the table. thereafter, subsequent transitions from sleep state to running state m ight result in different states for these pins. the opower-down stateo column defines the state of each pin during power-down mode (sleep state). this mode is defined as vcc3 turned off to the entire system, except for the PR31700 (rtc and interrupts alive) and any persistent me mory.
philips semiconductors preliminary specification PR31700 32-bit risc microprocessor 1998 may 13 17 table 2. PR31700 power-down pin usage PR31700 pin power-down control powerdown = (vccon & vcc3)* (reset state) pon* state 1st time power-up state power-down state d[31:0] mempowerdown low low low a[12:0] mempowerdown low low low ale low low low rd* powerdown low hi low we* mempowerdown low low low cas0* (we0*) mempowerdown low low low cas1* (we1*) mempowerdown low low low cas2* (we2*) mempowerdown low low low cas3* (we3*) mempowerdown low low low ras0* mempowerdown low low low ras1* (dcs1*) mempowerdown low low low dcs0* mempowerdown low low low dcke mempowerdown low low low dclkin dclkout mempowerdown low low low dqmh mempowerdown low low low dqml mempowerdown low low low dreq* powerdown & miopd[27] (1) pull-down in selectable dgrnt* powerdown & miopd[26] (0) low hi selectable sysclkin powerdown osc off osc on osc off sysclkout powerdown osc off osc on osc off c32kin osc on osc on osc on c32kout osc on osc on osc on bc32k powerdown & miopd[25] (1) pull-down in selectable vdat[3] module disable low low low vdat[2] module disable low low low vdat[1] module disable low low low vdat[0] module disable low low low cp module disable low low low load module disable low low low df module disable low low low frame module disable low low low dispon module disable low low low pwrcs low hi low pwrint pwrok onbutn cpures* pon* mbusclk module disable out low out low out low
philips semiconductors preliminary specification PR31700 32-bit risc microprocessor 1998 may 13 18 table 2. PR31700 power-down pin usage (continued) PR31700 pin power-down control powerdown = (vccon & vcc3)* (reset state) pon* state 1st time power-up state power-down state mbusdata module disable out low out low out low mbusint txd powerdown & miopd[24] (0) low low selectable rxd powerdown & miopd[23] (1) pull-down in selectable cs0* powerdown pull-down hi pull-down cs1* powerdown & miopd[22] (1) pull-down hi selectable cs2* powerdown & miopd[21] (1) pull-down hi selectable cs3* powerdown & miopd[20] (1) pull-down hi selectable mcs0* powerdown & miopd[19] (0) in in selectable mcs1* powerdown & miopd[18] (0) in in selectable mcs2* powerdown & miopd[17] (0) in in selectable mcs3* powerdown & miopd[16] (0) in in selectable chifs powerdown & miopd[31] (1) pull-down in selectable chiclk powerdown & miopd[30] (1) pull-down in selectable chidout powerdown & miopd[29] (1) pull-down in selectable chidin powerdown & miopd[28] (1) pull-down in selectable vcc3 powerdown pull-down pull-down io6 powerdown & iopd[6] (1) pull-down in selectable io5 powerdown & iopd[5] (1) pull-down in selectable io4 powerdown & iopd[4] (1) pull-down in selectable io3 powerdown & iopd[3] (1) pull-down in selectable io2 powerdown & iopd[2] (1) pull-down in selectable io1 powerdown & iopd[1] (1) pull-down in selectable io0 powerdown & iopd[0] (1) pull-down in selectable spiclk powerdown & miopd[15] (0) low low selectable spiout powerdown & miopd[14] (0) low low selectable spiin powerdown & miopd[13] (1) pull-down selectable sibsync powerdown low low low sibdout powerdown low low low sibdin powerdown pull-down pull-down sibmclk powerdown & miopd[12] (1) pull-down in selectable sibsclk powerdown low low low sibirq powerdown pull-down pull-down rxpwr powerdown low low low cardet powerdown pull-down pull-down irout powerdown low low low irin powerdown pull-down pull-down testaiu testcpu testin viddone module disable low low low
philips semiconductors preliminary specification PR31700 32-bit risc microprocessor 1998 may 13 19 table 2. PR31700 power-down pin usage (continued) PR31700 pin power-down control powerdown = (vccon & vcc3)* (reset state) pon* state 1st time power-up state power-down state cardreg* powerdown & miopd[11] (1) pull-down in selectable cardiowr* powerdown & miopd[10] (1) pull-down in selectable cardiord* powerdown & miopd[9] (1) pull-down in selectable card1csl* powerdown & miopd[8] (1) pull-down in selectable card1csh* powerdown & miopd[7] (1) pull-down in selectable card2csl* powerdown & miopd[6] (1) pull-down in selectable card2csh* powerdown & miopd[5] (1) pull-down in selectable card1wait* powerdown & miopd[4] (1) pull-down in selectable card2wait* powerdown & miopd[3] (1) pull-down in selectable carddir* powerdown & miopd[2] (1) pull-down in selectable miox[1] powerdown & miopd[1] (0) in in selectable miox[0] powerdown & miopd[0] (0) in in selectable endian nc[5:1] rsrv1 vdd34 each vss34 each
philips semiconductors preliminary specification PR31700 32-bit risc microprocessor 1998 may 13 20 function specifications outline the PR31700 consists of system support logic, integrated with the pr3901 processor core designed by philips. for details of the system support logic and the pr3901 processor core, refer to the PR31700 user's manual. pr3901 processor core the pr3901 is a philips-developed microprocessor core based on the r3000a risc architecture developed by mips technologies, inc. instructions all pr3901 processor core instructions are 32-bit instructions. apart from some coprocessor instructions, the instructions are upwardly compatible with the r3000a. the pr3901 processor core instructions can be classified into six types. ? load and store instructions transfer data between memory and general-purpose registers. ? computational instructions these include arithmetic, logical, shift, multiply, divide, and multiply-add instructions. the multiply-add instructions are extensions to the r3000a. the multiply instructions can also be used as three-operand instructions. ? special instructions used for system call or break point. ? jump and branch instructions change the control flow of a program. the branch-likely instruction is provided as an extension to the r3000a. ? coprocessor instructions perform operations for coprocessors. the r3000a lwcz and swcz instructions are reserved instructions in the pr3901 processor core. attempting execution generates a reserved instruction exception. note that the copz, ctcz and mtcz instructions are no-operation instructions, the cfcz and mfcz instructions load undefined data to general purpose registers (rt) in the PR31700. ? system control coprocessor instructions perform operations on the cp0 registers to manipulate the memory management and exception handling functions of the processor. registers the pr3901 processor core has following registers. ? 32 general purpose registers (32-bit) ? hi/lo registers hold the result of multiply and divide operation ? pc (program counter) ? cause register indicates the nature of the most recent exception ? epc (exception program counter) register holds the program counter at the time the exception occurred, indicating the address where processing is to resume after the exception processing is completed. ? status register holds the operating mode status (user mode or kernel mode), interrupt masking status, diagnosis status and other such information. ? badvaddr (bad virtual address) register holds the most recent virtual address for which a virtual address translation error occurred. ? prid register shows the revision number of the pr3901 processor core. cache register controls the instruction cache (reserved) and the data cache auto-lock bits. ? debug register control software debug exception. ? depc program counter for software debug exception. memory management the pr3901 processor core has a 4g-byte memory address space. the 4g-byte memory space consists of a 2g-byte user area and a 2g-byte kernel area. the kernel area contains a cache area and an uncache area.the pr3901 processor core provides a full-featured memory management unit (mmu) utilizing an on-chip translation lookaside buffer (tlb). the on-chip tlb majur characteristics are : ? 32 x 64-bit wide entries ? fully associative ? 2 entry micro tlb for instruction address translation ? instruction address translation accesses full tl after micro-tlb miss ? data address translation accesses full tlb pipeline the pr3901 processor core pipeline consists of five stages. the pipeline configuration enables the pr3901 processor core to execute nearly all instructions in one clock. cache the PR31700 incorporates a 4k-byte instruction cache and a 1k-byte data cache. the instruction cache is direct-mapped with a block size of 16 bytes. the data cache uses two-way set-associative mapping with a block size of four bytes. the data cache has a lock function that locks data in one direction. the write-through method is used to write data back to memory. dsp function the pr3901 processor core has a high-speed multiplier/accumulator and supports 32-bit multiplier operations, with 64-bit accumulator in one cycle.
philips semiconductors preliminary specification PR31700 32-bit risc microprocessor 1998 may 13 21 peripheral functions clock generator the PR31700 uses an internal pll and an external crystal oscillator to generate a clock with eight times the input clock frequency. the pll oscillation can be halted externally to reduce power dissipation. write buffer the PR31700 incorporates a four-stage write buffer. bus interface unit (biu) module the PR31700 has a bus interface unit with the following features. ? supports 2 banks of sdram and/or dram / hdram 8-bit or 16-bit sdram configuration 16-bit or 32-bit dram configuration 16-bit or 32-bit hdram configuration 4 mbit, 16 mbit and 64 mbit parts supported page mode reads and writes supported independent refresh counters for each bank self refreshing parts supported to retain memory when system is powered down ? 4 general purpose chip selects (cs3*cs0*) 16-bit or 32-bit ports programmable wait states read page mode ? 4 general purpose chip selects (mcs3*mcs0*) 16-bit ports programmable wait states read page mode ? 2 full pcmcia slots 16-bit ports iord and iowr provided to support i/o cards wait signal supported system interface unit (siu) module the PR31700 has a system interface unit with the following features. ? multi-channel 32-bit dma controller ? independent dma controller for video, sib to/from betty audio/telecom codecs, high-speed serial port, ir, uart, and general purpose uart ? address decoding for the internal registers clock module the PR31700 has a clock module with the following features. ? the PR31700 supports system-wide single crystal configuration, besides the 32 khz rtc xtal (reduces cost, power, and board space) ? common crystal rate divided to generate clock for cpu, video, sound, telecom, uarts, etc. ? independent enabling or disabling of individual clocks under software control, for power management concentration highway interface (chi) module the PR31700 has a chi module with the following features. ? high-speed serial concentration highway interface (chi) contains logic for interfacing to external full-duplex serial time-division-multiplexed (tdm) communication peripherals ? supports isdn line interface chips and other pcm/tdm serial devices ? chi interface is programmable (number of channels, frame rate, bit rate, etc.) to provide support for a variety of formats ? supports data rates up to 4.096 mbps ? independent dma support for chi receive and transmit interrupt module the PR31700 has an interrupt module with the following features. ? contains logic for individually enabling, reading, and clearing all PR31700 interrupt sources ? interrupts generated from internal PR31700 modules or from edge transitions on external signal pins io module the PR31700 has an io module with the following features. ? contains support for reading and writing the 7 bi-directional general purpose io pins and the 32 bi-directional multi-function io pins ? each io port can generate a separate positive and negative edge interrupt ? independently configurable io ports allow the PR31700 to support a flexible and wide range of system applications and configurations ir module the PR31700 has an ir module with the following features. ? ir consumer mode allows control of consumer electronic devices such as stereos, tvs, vcrs, etc. programmable pulse parameters external analog led circuitry ? irda communication mode not compatible with general magic cap devices allows communication with other irda devices such as fax machines, copiers, printers, etc. supported by the uart module within the PR31700 external analog receiver preamp and led circuitry data rate = up to 115 kbps at 1 meter ? ir fsk communication mode compatible with generai magic cap devices supported by the uart module within the PR31700 external analog ir chip(s) perform frequency modulation to generate the desired ir communication mode protocol data rate = up to 36000 bps at 3 meters ? carrier detect state machine periodically enables ir receiver to check if a valid carrier is present
philips semiconductors preliminary specification PR31700 32-bit risc microprocessor 1998 may 13 22 power module the PR31700 has a power module with the following features. ? power-down modes for individual internal peripheral modules ? serial (spi port) power supply control interface supported ? power management state machine has 3 states: running, dozing and sleep serial interconnect bus (sib) module the PR31700 has a sib module with the following features. ? the PR31700 contains holding and shift registers to support the serial interface to the ucb1200 asic and/or other optional codec devices ? synchronous, frame-based protocol ? the PR31700 always master source of clock and frame frequency and phase; programmable clock frequency ? each sib frame consists of 128 clock cycles, further divided into 2 subframes or words of 64 bits each (supports up to 2 devices simultaneously) ? independent dma support for audio receive and transmit, telecom receive and transmit ? supports 8-bit or 16-bit mono telecom formats ? supports 8-bit or 16-bit mono or stereo audio formats ? independently programmable audio and telecom sample rates ? cpu read/write registers for subframe control and status serial peripheral interface (spi) module the PR31700 has an spi module with the following features. ? provides interface to spi peripherals and devices ? full-duplex, synchronous serial data transfers (data in, data out, and clock signals) ? the PR31700 supplies dedicated chip select and interrupt for an spi interface serial power supply ? 8-bit or 16-bit data word lengths for the spi interface ? programmable spi baud rate timer module the PR31700 has a timer module with the following features. ? real time clock (rtc) and timer ? 40-bit counter (30.517 s granularity); maximum uninterrupted time = 388.36 days ? 40-bit alarm register (30.517 s granularity) ? 16-bit periodic timer (0.868 s granularity); maximum timeout = 56.8 ms ? interrupts on alarm, timer, and prior to rtc roll-over uart module the PR31700 has a uart module with the following features. ? 2 independent full-duplex uarts ? programmable baud rate generator ? uart a port used for serial control interface to external ir module ? uart b port used for general purpose serial control interface ? uart a and uart b dma support for receive and transmit video module the PR31700 has a video module with the following features. ? bit-mapped graphics ? supports monochrome, grey scale, or color modes ? time-based dithering algorithm for gray scale and color modes ? supports multiple screen sizes ? supports split and non-split displays ? variable size and relocatable video buffer ? dma support for fetching image data from video buffer
philips semiconductors preliminary specification PR31700 32-bit risc microprocessor 1998 may 13 23 electrical characteristics absolute maximum ratings v ss = 0 v (gnd) symbol parameter limits unit v dd power supply voltage v ss 0.5 to 4.5 v v in input voltage v ss 0.5 to v dd + 0.5 v t stg storage temperature range 55 to +125 c pd maximum dissipation (t amb = 70 c) 1 w note: 1. using an lsi at specifications higher than the maximum ratings can cause permanent damage to the lsi. for normal operation, use under the recommended operating conditions. exceeding the recommended operating conditions may affect the reliability of the lsi. recommended operating conditions v ss = 0 v (gnd) symbol parameter limits unit symbol parameter min typ max unit v dd power supply voltage 3.0 3.3 3.6 v t opr operating temperature range 0 70 c
philips semiconductors preliminary specification PR31700 32-bit risc microprocessor 1998 may 13 24 dc characteristics (t amb = 0 c to 70 c, v dd = 3.3v 0.3v) symbol parameter conditions limits unit symbol parameter conditions min typ max unit i dd operating current v in = v dd or v ss ; v dd = max i oh = i ol = 0 110 130 ma i dds, p static current v in = v dd or v ss ; v dd = max i oh = i ol = 0 ma sleep mode & rtc stop mode 10 100 m a i dds, q v in = v dd or v ss ; v dd = max i oh = i ol = 0 ma sleep mode & rtc running mode 20 120 m a i in input leakage current v in = v dd or v ss 10 10 m a v ih1 input voltage 1 v dd = 3.6v v dd 0.8 v dd + 0.3 v v il1 input voltage 1 v dd = 3.0v 0.3 v dd 0.2 v v ih2 input voltage 2 v dd = 3.6v 2.4 v dd + 0.3 v v il2 input voltage 2 v dd = 3.0v 0.3 0.6 v v oh1 output voltage 3 v dd = 3.0v; i oh = 4ma v dd 0.6 v v ol1 output voltage 3 v dd = 3.0v; i ol = 4ma v dd + 0.4 v v oh2 output voltage 4 v dd = 3.0; i oh = 8ma v dd 0.6 v v ol2 output voltage 4 v dd = 3.0; i ol = 8ma v dd + 0.4 v v oh3 output voltage 5 v dd = 3.0; i oh = 16ma v dd 0.6 v v ol3 output voltage 5 v dd = 3.0; i ol = 16ma v dd + 0.4 v v oh4 output voltage 6 v dd = 3.0; i oh = 24ma v dd 0.6 v v ol4 output voltage 6 v dd = 3.0; i ol = 24ma v dd + 0.4 v i ihp input current (pulldown resister) v dd = max; vin = v dd 20 120 m a notes: 1. sysvlkin 2. other inputs 3. d[31:0], ras0*, ras1*, dcs0*, dcke*, dqmh, dqml, dreq*, dgrnt*, bc32k, vdat[3:0], cp, load, df, frame, dispon, viddone, pwrcs, txd, rxd, cs3 ~ o*,chifs, chiclk, chidout, chidin, io[6;0], spiclk, spiout, spiin, sibsync, sibdout, sibmclk, sibclk, rwpwr, irout, card1wait*, card2wait*, miox[2;0] 4. a[12:], ale, rd*, we* cas3 ~ o*, cardreg*, cardiowr*, card1csl*, card1csh*, card2csl*, card2csh* 5. dclkout 6. mbusclk, mbusdata
philips semiconductors preliminary specification PR31700 32-bit risc microprocessor 1998 may 13 25 crystal oscillator characteristics sysckin sysclkout x 1 tal recommended 9.216mhz crystal nihon dempa kogyo co., ltd: at51 c in c out sn00191 PR31700 figure 4. 10mhz crystal symbol parameter recommended value unit symbol parameter min. max. unit f in crystal oscillator frequency 825 10 mhz f in crystal oscillator frequency 8 . 25 10 mhz c in , c out external capacitors 10 33 pf c32kin c32kout x 1 tal recommended 32.768khz crystal kyocera corporation: kf38g c in c out sn00192 PR31700 figure 5. 32 khz crystal symbol parameter recommended value unit symbol parameter min. max. unit c in , c out external capacitors 10 33 pf
philips semiconductors preliminary specification PR31700 32-bit risc microprocessor 1998 may 13 26 electrical specifications (v ss = 0v, v dd = 3.3v) parameter symbol condition min. typ. max. unit crystal stabilization time 9.216mhz t sta10m f = 8.25mhz10mhz x'tal : at51 cin = cout = 10pf33pf - - 10 ms crystal stabilization time 32.768khz t sta32k f = 32khz x'tal : kf38g cin = cout = 10pf33pf - - 2 s PR31700 timing 0.8v 2.0v delay setup hold 2.2v 0.8v 2.2v 0.8v 2.2v 0.8v outputs inputs 0.8v cc 0.2v cc sn00165 figure 6. definition of ac specification
philips semiconductors preliminary specification PR31700 32-bit risc microprocessor 1998 may 13 27 ac characteristics the following operating conditions apply to all values specified in this section. t amb = 0 c to 70 c, v dd = 3.3 0.3v, external capacitance = 40pf item parameter rising / falling min. max. unit 1 dclkout high time - 5.4 - ns 2 dclkout low time - 5.4 - ns 3 dclkout period - 13.5 - ns 4 delay dclkout to ale rising - 4 ns 4 delay dclkout to ale falling - 3 ns memory interface 4 delay dclkout to a[12:0] - - 8 ns 4 delay dclkout to d[31:16] - - 8 ns 4 delay dclkout to d[15:0] - 1.5 8 ns 4 delay dclkout to cs30* rising - 10 ns 4 delay dclkout to cs30* falling - 10 ns 4 delay dclkout to rd* rising - 8 ns 4 delay dclkout to rd* falling - 7 ns 4 delay dclkout to we* rising - 5 ns 4 delay dclkout to we* falling - 4 ns 4 delay dclkout to cas30* rising - 2.5 ns 4 delay dclkout to cas30* falling - 2.5 ns 4 delay dclkout to cardxcsx* rising - 9 ns 4 delay dclkout to cardxcsx* falling - 8 ns 4 delay dclkout to carddir* rising - 12 ns 4 delay dclkout to carddir* fallmng - 11 ns 4 delay dclkout to cardreg* rising - 9 ns 4 delay dclkout to cardreg* fatting - 10 ns 4 delay dclkout to cardiord* rising - 10 ns 4 delay dclkout to cardiord* falling - 9 ns 4 delay dclkout to cardiowr* rising - 9 ns 4 delay dclkout to cardiowr* falljng - 9 ns 4 delay dclkout to ras0* rising - 6 ns 4 delay dclkout to ras0* falling - 6 ns 4 delay dclkout to ras1* rising 1.5 8 ns 4 delay dclkout to ras1* falling 1.5 9 ns 4 delay dclkout to dqmh/l rising 1.5 8 ns 4 delay dclkout to dqmh/l falling 1.5 9 ns 4 delay dclkout to dcs0* rising 1.5 7 ns 4 delay dclkout to dcs0* falling 1.5 6 ns 4 delay dclkout to dcke rising 1.5 8 ns 4 delay dclkout to dcke falling 1.5 8 ns 4 delay dclkout to mcs30* rising - 10 ns 4 delay dclkout to mcs30* falling - 10 ns 5 d[31 : 16] to dclkin setup time - 1 - ns
philips semiconductors preliminary specification PR31700 32-bit risc microprocessor 1998 may 13 28 item parameter rising / falling min. max. unit 6 d[31 : 16] to dclkin hold time - 2 - ns 5 d[15:0] to dclkin setup time - 0 - ns 6 d[15:0] to dclkin hold time - 2.5 - ns 7 dclkout to dclkin board delay time - 0 3 ns 1 2 4 dclkout memory outputs sn00168 3 figure 7. memory output and clock timing 6 dclkin memory 5 sn00169 inputs figure 8. memory input timing dclkout dclkin 7 sn00170 figure 9. dclkout to dclkin
philips semiconductors preliminary specification PR31700 32-bit risc microprocessor 1998 may 13 29 chi characteristics item parameter rising / falling min. max. unit 1 chiclk high time - 100 - ns 2 chiclk low time - 100 - ns 3 chiclk period - 225 - ns 4 delay chiclk rising to chidout(master) rising - 5 ns 4 delay chiclk rising to chidout(master) falling - 5 ns 7 delay chiclk falling to chidout(master) rising - 5 ns 7 delay chiclk falling to chidout(master) falling - 5 ns 4 delay chiclk rising to chifs(master) rising - 5 ns 4 delay chiclk rising to chifs(master) falling - 5 ns 7 delay chiclk falling to chifs(master) rising - 5 ns 7 delay chiclk falling to chifs(master) falling - 5 ns 4 delay chiclk rising to chidout(slave) rising - 15 ns 4 delay chiclk rising to chidout(slave) falling - 15 ns 7 delay chiclk falling to chidout(slave) rising - 15 ns 7 delay chiclk falling to chidout(slave) falling - 15 ns 4 delay chiclk rising to chifs(slave) rising - 15 ns 4 delay chiclk rising to chifs(slave) falling - 15 ns 7 delay chiclk falling to chifs(slave) rising - 15 ns 7 delay chiclk falling to chifs(slave) falling - 15 ns 5 chidin to chiclk rising setup time(master) - 20 - ns 6 chidin to chiclk rising hold time(master) - 20 - ns 8 chidin to chiclk falling setup time(master) - 20 - ns 9 chidin to chiclk falling hold time(master) - 20 - ns 5 chifs to chiclk rising setup time(slave) - 20 - ns 6 chlfs to chiclk rising hold time(slave) - 20 - ns 8 chifs to chiclk falling setup time(slave) - 20 - ns 9 chifs to chiclk falling hold time(slave) - 20 - ns 5 chidin to chiclk rising setup time(slave) - 20 - ns 6 chidin to chiclk rising hold time(slave) - 20 - ns 8 chidin to chiclk falling setup time(slave) - 20 - ns 9 chidin to chiclk falling hold time(slave) - 20 - ns
philips semiconductors preliminary specification PR31700 32-bit risc microprocessor 1998 may 13 30 1 2 4 chiclk outputs sn00171 chi 3 figure 10. chi output and clock timing (chitxedge=1) 6 chiclk chi 5 sn00172 inputs figure 11. chi input timing (chirxedge=1) 7 chiclk chi sn00173 outputs figure 12. chi output and clock timing (chitxedge=0) 9 chiclk 8 sn00174 inputs chi figure 13. chi input timing (chirxedge=0)
philips semiconductors preliminary specification PR31700 32-bit risc microprocessor 1998 may 13 31 sib characteristics item parameter rising / falling min. max. unit 1 sibmclk high time - 20 - ns 2 sibmclk low time - 20 - ns 3 sibmclk period - 50 - ns 4 delay sibmclk (master) to sibsclk rising - 5 ns 5 delay sibmclk (master) to sibsclk falling - 5 ns 6 delay sibsclk rising to sibsync rising - 2 ns 6 delay sibsclk rising to sibsync falling - 2 ns 6 delay sibsclk rising to sibdout rising - 2 ns 6 delay sibsclk rising to sibdout falling - 2 ns 7 sibdin to sibsclk rising setup time - 20 - ns 8 sibdin to sibsclk rising hold time - 0 - ns 1 3 2 5 sibmclk sibsclk 4 sn00175 figure 14. sib clk timing 6 sibsclk outputs 8 7 sibdin sn00176 sib figure 15. sib timing
philips semiconductors preliminary specification PR31700 32-bit risc microprocessor 1998 may 13 32 spi characteristics item parameter rising / falling min. max. unit 1 spiclk high time - 120 - ns 2 spiclk low time - 120 - ns 3 spiclk period - 250 - ns 4 delay spiclk rising to spiout rising - 5 ns 4 delay spiclk rising to spiout falling - 5 ns 7 delay spiclk falling to spiout rising - 5 ns 7 delay spiclk falling to spiout falling - 5 ns 8 spiin to spiclk rising setup time - 15 - ns 9 spiin to spiclk rising hold time - 15 - ns 5 spiin to spiclk falling setup time - 15 - ns 6 spiin to spiclk falling hold time - 15 - ns 4 spiclk spiout 6 5 spiin 2 1 3 sn00177 figure 16. spi timing (phapol = 1) 7 spiclk spiout 9 8 spiin sn00178 figure 17. spi timing (phapol = 0)
philips semiconductors preliminary specification PR31700 32-bit risc microprocessor 1998 may 13 33 video characteristics item parameter rising / falling min. max. unit 1 load pule width - 100 1600 ns 2 delay load falling to frame - 100 3200 ns 3 delay load falling to df - 100 3200 ns 4 delay load falling to cp - 100 3200 ns 5 delay cp rising to vdat[3:0] - - 5 ns 6 vdat to cp rising setup - 15 25 ns 7 vdat to cp rising hold - 15 25 ns note: 1. values shown assume a 75mhz clock for the cpu. min and max values are programmable using video control registers. 2 frame 1 load df 3 cp 4 5 vdat[3:0] sn00179 figure 18. video timing, 4-bit non-split lcd 7 cp vdat[3:0] 6 sn00180 figure 19. video data timing, 4-bit split lcd and 8-bit non-split lcd
philips semiconductors preliminary specification PR31700 32-bit risc microprocessor 1998 may 13 34 power characteristics item parameter rising / falling min. max. unit 1 vstandby to pon* rising - 50 - ms 2 vstandby to onbutn delay time - 2 - s vstandby onbutn /pon 1 2 sn00181 figure 20. power on timing diagram cpu reset characteristic item parameter rising / falling min. max. unit 1 cpures* low time - 10 - ns cpures* 1 sn00182 figure 21. cpu reset timing diagram
philips semiconductors preliminary specification PR31700 32-bit risc microprocessor 1998 may 13 35 lqfp208: 208-pin plastic low profile quad flat package
philips semiconductors preliminary specification PR31700 32-bit risc microprocessor 1998 may 13 36 definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the dev ice at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limi ting values for extended periods may affect device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support e these products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use i n such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors ass umes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or m ask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right in fringement, unless otherwise specified. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 ? copyright philips electronics north america corporation 1998 all rights reserved. printed in u.s.a. date of release: 05-98 document order number: 9397 750 03867
data sheet status objective specification preliminary specification product specification product status development qualification production definition [1] this data sheet contains the design target or goal specifications for product development. specification may change in any manner without notice. this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. this data sheet contains final specifications. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. data sheet status [1] please consult the most recently issued datasheet before initiating or completing a design.

▲Up To Search▲

Price & Availability of PR31700

	To Download PR31700 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .